The present invention relates to a circuit for reproducing and demodulating a modulated digital signal which was modulated with a certain modulation system, and, in particular, a circuit for reproducing and demodulating for example MFM (Modified Frequency Modulation), EFM (Eight-to-Fourteen Modulation), and 3PM (Three Position Modulation) pulse signals or the like into an original pulse time-series signal with a certain accuracy.
There has been disclosed a prior art demodulating circuit for demodulating the MFM signals in Japanese Patent Publication No. 38884/79 published on Nov. 24, 1979, which was filed by the same assignee of the present application. An edge pulse to be generated at a rising edge and a falling edge, respectively, of the MFM pulse, and a clock pulse signal having a period T/2 (where T represents the shortest pulse width T of the MFM pulse signal) which is synchronized in phase with the rising edge and the falling edge of the MFM pulse signal, are inputted to the prior art demodulating circuit. The edge pulse signal is used to reset or initialize a counter which is then ready for counting the clock pulses. When the number of the clock pulses as counted becomes equal to 4, a reset pulse is produced. In this connection, it is to be noted that the MFM pulse signal is composed of only three types of pulses having the pulse widths or durations T, 1.5 T and 2T, respectively, wherein the maximum pulse width 2T occurs in correspondence to a bit pattern "101" of the original digital information. Accordingly, the reset pulse appearing at the output of the counter is produced only in response to the bit pattern of "101".
By the way, the edge pulse signal is also supplied to a monostable multivibrator which is triggered by the falling edge of the edge pulse, whereby pulses each having a pulse width equal to T/2 are produced. The clock pulse signal of the period T/2 undergoes a division-by-2 operation in a frequency divider which is adapted to be reset by the reset pulse supplied from the counter, resulting in a demodulating clock pulse signal being outputted. A D-type flip-flop is supplied with the pulse signal outputted from the monostable multivibrator and the demodulating clock signal from the frequency divider, to thereby latch the pulse signal outputted from the monostable multivibrator in response to the rising edge of the demodulating clock signal. The output signal from the D-type flip-flop thus constitutes a demodulated output signal of NRZ (non-return-to-zero) form which is in synchronism with the demodulating clock signal and is produced at a demodulated signal output terminal for external utilization.
As will be appreciated from the above description of the hitherto known MFM pulse signal demodulating circuit, because the output pulse signal produced by the monostable multivibrator is latched by the demodulating clock signal, errors or temperature-depending variations in the values of the CR-elements which determine the time constant of the monostable multivibrator will be reflected as variations or changes in the pulse width of the output pulse signal or as a reduction in the margin or tolerance of timing for the demodulation, which is a disadvantage. When the timing margin is to be as large as possible, then adjustment of the time constant is required, which is also a disadvantage. Further, the known MFM pulse signal demodulating circuit suffers a drawback in that pins for connection for externally mounted capacitors have to be provided for implementation in an LSI circuit.
Furthermore, the hitherto known MFM signal demodulating circuit suffers a drawback in that code errors are produced in the demodulated MFM signal when the phase of the MFM signal is inverted during an interval or duration in which a drop-out occurs in the MFM signal to be reproduced.